A semiconductor integrated circuit includes logic elements 1 (FIG. 11) for performing an operation and controlling the operation, and sequential circuit elements 5 (also referred to as flip-flops) (FF1, FF2 in FIG. 11) for synchronizing an operation of a logic element group 3. Each flip-flop 5 is supplied with a clock signal CLK that cyclically oscillates. Data held by the flip-flop 5 is then supplied to the logic element 1 in accordance with a rising edge or a falling edge of the clock signal CLK. The logic element 1 then performs an operation and controls the operation by use of the supplied data as an input, to store a result thereof into the flip-flop 5. The above process is repeatedly performed in accordance with the rising edge of or the falling edge of the clock signal CLK that cyclically changes.
A design process of the semiconductor integrated circuit performs: analyzing a delay in the clock signal CLK that is supplied to the flip-flop 5; simulating operations of the circuit with reference to the clock signal CLK; and verifying whether the circuit can operate with normal timing.
Patent Document 1 discloses an example of timing verification method for verifying operation timing in view of a voltage drop of power-supply wiring in a semiconductor integrated circuit. The timing verification method of Patent Document 1 includes: setting a maximal value of a power-supply voltage drop level which is permitted in a semiconductor chip as a target power-supply voltage drop level; calculating a power-supply voltage drop level for timing verification based on the target power-supply voltage drop level; performing a first timing verification in view of a delay fluctuation according to the power-supply voltage drop level; thereafter comparing a power-supply voltage drop level of each cell with the power-supply voltage drop level for the timing verification, the power-supply voltage drop level being obtained from an analysis result of a power supply net analysis; and recalculating the delay fluctuation in accordance with the power-supply voltage drop level of the cell having a different level in a result of the comparison to perform a second timing verification.
Further, Patent Document 2 discloses an example of semiconductor design supporting apparatus that performs a logic simulation analysis/STA analysis in view of noise. The semiconductor design supporting apparatus of Patent Document 2 is a semiconductor design supporting apparatus provided with a power-supply noise level library and an output signal change level library, and the power-supply noise level library stores power-supply noise data obtained by analyzing power-supply noise generated in an input/output unit. Further, the output signal change level library stores output signal change data showing a signal waveform that changes in response to the power-supply noise data. This semiconductor design supporting apparatus disclosed in Patent Document 2 generates a noise corresponding I/O layout model showing the input/output unit of a semiconductor device which corresponds to the power-supply noise, and predicts timing for operation of the semiconductor device based on the output signal change data and the noise corresponding I/O layout model.
Further, Patent Document 3 discloses a logic circuit operation verifying apparatus, capable of verifying a power-supply voltage drop and a ground bounce, which are problematic in a large-scaled CMOS LSI, in a design stage of a chip before manufacturing thereof, to obtain an indicator for optimizing power-supply wiring, and further to detect a margin of a propagation delay caused by the power-supply voltage drop or the ground bounce.
Patent Document 4 discloses an apparatus and a method for simulating a semiconductor integrated circuit, which reflect time-series voltage fluctuation information to a delay simulation, to obtain a highly accurate delay simulation result.
Patent Document 5 discloses an apparatus and a method for calculating a delay in a semiconductor integrated circuit and an apparatus and a method for verifying timing thereof, which calculate a voltage drop due to power-supply wiring and consider the voltage drop with respect to each kind of elements, to perform highly reliable delay calculation and timing verification.
Other than this, Patent Documents 6 to 12 disclose examples of the timing verification methods for verifying operation timing in view of a voltage drop of power-supply wiring in a semiconductor integrated circuit.